In recent years, the development of the electronic industry, particularly the semiconductor industry, advances rapidly. Thereby, the size of a chip is getting smaller with more functions. Accordingly, to utilize the devices in a chip effectively and to make them function within limited space are the objectives of the semiconductor industry. The electrostatic-discharge (ESD) protection devices used in a chip are generally realized by connecting the pad in a chip to a dummy metal-oxide-semiconductor field-effect transistor (MOSFET) for preventing damage caused by large currents generated by static charges entering the internal circuitry of the chip.
FIG. 1 shows a structural schematic diagram of a conventional N-type MOSFET (NMOSFET) for ESD protection. As shown in the figure, a P-type substrate 1′ is provided and a gate oxide layer 2′ is set up thereon. In addition, a polysilicon layer 3′ is set up on the gate oxide layer 2′ as a gate electrode, and is coupled to the ground. In the P-type substrate 1′, a first N-type doping region 10′ and a second N-type doping region 12′ are set up on both sides of the gate oxide layer 2′ for being a source electrode and a drain electrode. The first N-type doping region 10′ is coupled to the ground, while the second N-type doping region 12′ is coupled to a pad 4′. When the current produced by static charges enters the chip through the pad 4′, it will be led to the ground by way of the PN junction formed by the second N-type doping region 12′ and the P-type substrate 1′ of the NMOSFET, and of the bipolar-transistor effect produced by the first N-type doping region 10′, the P-type substrate 1′, and the second N-type doping region 12′. Thereby, ESD protection is achieved.
The structure described above has superior effect on ESD protection. Nevertheless, when the chip operates, the MOSFET is not functioning, which is regrettable in terms of design of semiconductor chips. In general, if voltage-stabilizing effect is needed between the power supply and the ground, an extra capacitor is needed with the expense of extra chip space. Thereby, the size of the chip is increased, and hence the cost thereof is increased as well.
Accordingly, a novel MOSFET and a method for manufacturing the same are proposed for providing ESD protection as well as voltage-stabilizing effect between the power supply and the ground.